Many computing systems, such as personal computers, automotive and airplane control, cellular phones, digital cameras, and hand-held communication devices, use non-volatile memories to store either data, or code or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories ("EEPROMs") and flash Erasable and Electrically Programmable Read-Only Memories ("flash EPROMs" or "flash memories").
Non-volatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
Writability enables the computing system to be reprogrammed. This is useful, for example, for upgrading the system, or for correcting bugs in the code.
Prior art flash EPROMs can be used to store both code and data. In one prior art usage, code is stored in certain blocks of the flash EPROM, and data is stored in other blocks of the flash EPROM. This allows for erasing one block without disturbing the contents of a different block. Additionally, some flash EPROMs provide for data blocks and code blocks to have different sizes.
Although it is possible to store both code and data in a flash EPROM and execute code provided directly from the flash EPROM to a processor, a problem arises when a flash EPROM is used in a system that requires quick servicing of code fetches. This is due to the long latency times for program cycles and erase cycles. For one prior art flash EPROM, a program cycle to write a byte of data takes a maximum program cycle time of 100 microseconds in order to guarantee that the program cycle performs correctly. Erasing a 8 kilobyte block of data in a flash EPROM may take up to a maximum erase cycle time of 3 seconds to completely erase the entire block of data.
If a processor were performing a program cycle to write data to the flash EPROM, and subsequently the processor requested that the flash EPROM perform a read cycle in order to perform a code fetch, i.e., a read of code, to get new instructions for the processor to execute, the read cycle may be delayed up to 100 microseconds waiting for the program cycle to complete. This causes the processor to stall: the processor remains idle until it receives new instructions. Such a delay to read code would be unacceptable in a system that requires code fetches to be performed in less time than the maximum program cycle time.
FIG. 1 shows a prior art representation of a system comprising a processor 100, a volatile memory 102, and a flash EPROM 104 coupled together via a bus 108. The volatile memory 102 and the flash EPROM 104, however, could be coupled to the processor 100, via separate buses. The flash EPROM includes both code and data, wherein the code is executable by the processor. The code of the flash EPROM is shadowed, or copied, to the volatile memory, which may be either dynamic random access memory (DRAM) or static random access memory (SRAM). After the code is shadowed in the volatile memory, if the flash EPROM is performing a program cycle and the processor generates a code fetch request, then the processor can satisfy the code fetch request by reading the requested code from the volatile memory. The processor does not need to wait for the flash EPROM to finish its program cycle in order to perform a code fetch.
This scheme, however, may be expensive if the size of the code stored in the flash EPROM is large, since the DRAM would need to be large enough to store the entire code block in order to overcome the program cycle latency. One example of a system which might use the configuration shown in FIG. 1 is a personal computer (PC).
FIG. 2 shows a prior art system including a processor 100, a volatile memory 102, a flash EPROM 104, and an EEPROM 106. In this prior art system, the EEPROM 106 stores data and the flash EPROM 104 stores code. The DRAM/SRAM 102 is used for temporarily storing data before providing the data to the EEPROM 106, i.e., the DRAM/SRAM 102 serves as a buffer between the processor and the EEPROM 106.
FIG. 3 shows another prior art system in which the EEPROM 106 stores code, and the flash EPROM 104 stores data. The DRAM/SRAM 102 is used as a temporary buffer between the processor and the flash EPROM 104.
Because the erase operation has such a long latency time, a prior art flash EPROM includes an erase suspend command. When an erase suspend command is written to the flash EPROM, the flash EPROM suspends the erase operation that is being performed. Other operations may then be performed on the flash EPROM. Subsequently, when an erase resume command is written to the flash EPROM, the flash EPROM resumes the erase operation from where its operation was suspended due to the erase suspend command. One implementation of erase suspend circuitry is described in U.S. Pat. No. 5,355,464, entitled "Circuitry And Method For Suspending The Automated Erasure Of A Non-Volatile Semiconductor Memory," by Fandrich et al., and issued to the common assignee of this application.
FIG. 4 shows a prior art representation of a flash EPROM 10. The flash EPROM includes a command register 20, memory array control circuitry 40, and memory array 50.
A number of data input/output (I/O) pins 12 are coupled from pins of the flash EPROM to a command register 20. The number of data I/O pins 12 is usually 8 pins or 16 pins, which matches the size of data to be stored to the flash EPROM. The data I/O pins also allow commands to be written to the command register 20. For example, for one prior art flash EPROM, the command register 20 includes circuitry for decoding the following commands: (1) erase, (2) erase suspend, (3) erase resume, (4) program, (5) read, and (6) read status. A write enable (WE#) pin 30 is coupled to provide an input to the command register 20.
The command register 20 is coupled to memory array control circuitry 40 via signal lines 78a-n. The memory array control circuitry 40 includes a status register 42. The memory array control circuitry 40 also includes read circuitry, row and column decoder circuitry for accessing and providing data to cells in the memory array 50, and a write state machine, which includes program and erase circuitry. The memory array control circuitry 40 provides the appropriate signals to access the memory array 50 for carrying out the commands provided by the command register 20. The memory array control circuitry 40 receives an address input 44 from address pins of the flash EPROM. A command reset signal 48 is coupled from the memory array control circuitry 40 to the command register 20.
The memory array is coupled to provide data to an output multiplexer 60 for providing data to the data I/O pins 12 of the flash EPROM responsive to a read operation. The status register 42 is also coupled to provide data to the output multiplexer 60 for providing status data to the data I/O pins 12 of the flash EPROM responsive to a read status operation. The status register 42 provides information about the current operation being executed by the flash EPROM. The memory array control circuitry 40 controls the output multiplexer 60 based upon the commands provided to it from the command register 20. The memory array control circuitry 40 selects the status register output to pass through the output multiplexer 60 in response to a read status operation, and the memory array control circuitry selects the memory array output to pass through the output multiplexer 60 in response to a read operation.
In a prior art flash EPROM, a Ready/Busy (RY/BY#) pin 62 of the flash EPROM provides a status indicator of whether the flash EPROM is busy or not. The RY/BY# pin is "low" to indicate a busy state, which signifies that the flash EPROM is performing a block erase operation or a byte write operation. The RY/BY# pin is "high" to indicate a ready state, which signifies that the flash EPROM is ready for new commands, block erase is suspended, or the device is in a powerdown mode. The status register 42 is coupled to provide an output to the RY/BY# pin 62.
Additionally, a supply voltage Vcc, ground potential Vss, and a programming voltage Vpp are provided to the flash EPROM 10.
FIG. 5 shows a prior art block diagram of the command register 20 and the memory array control circuitry 40 of the flash EPROM 10. The command register 20 includes a command decoder 70 and command latches 76a-n. The command latches include an erase latch 76a, an erase suspend latch 76b, an erase resume latch 76c, a program latch 76d, a read latch 76m, and a read status latch 76n.
The command decoder 70 decodes the commands it receives from the data I/O pins 12. Each of the commands are provided to an associated command latch 76a-n via the signal lines 72a-n. The command latches 76a-n latch the signals from the command decoder upon assertion of the write enable (WE#) pin 30. The command latches 76a-n provide the decoded command to the memory array control circuitry 40 via the signal lines 78a-n.
The memory array control circuitry includes erase circuitry 90, program circuitry 94, read circuitry 96, and read status circuitry 98. Erase circuitry 90 includes erase suspend circuitry 92. Read status circuitry 98 is coupled to the status register 42.
The erase latch 76a, erase suspend latch 76b, and the erase resume latch 76c are coupled to erase circuitry 90. The erase suspend latch 76b and erase resume latch 76c are coupled to erase suspend circuitry 92 within the erase circuitry 90.
The program latch 76d is coupled to program circuitry 94. The read latch 76m is coupled to read circuitry 96, and the read status latch 76n is coupled to read status circuitry 98.
The memory array control circuitry 40 is coupled to provide one or more command reset signals 48 to the command decoder 70 for clearing the command latches 76a-n. The command decoder 70 uses the command reset signals 48 to clear the command latches 76a-n via command latch reset signals 74a-n. For one implementation, there are individual command latch reset signals 74a-n coupled to each command latch 76a-n. For another implementation, one command latch reset signal is coupled to all of the command latches.